SDRAM
AS4SD8M16
Austin Semiconductor, Inc.
Data from any READ burst may be truncated with a cated with, a PRECHARGE command to the same bank (pro-
subsequent WRITE command, and data from a fixed-length vided that auto precharge was not activated), and a full-page
READ burst may be immediately followed by data from a burst may be truncated with a PRECHARGE command to the
WRITE command (subject to bus turn-around limitations). The same bank. The PRECHARGE command should be issued x
WRITE burst may be initiated on the clock edge immediately cycles before the clock edge at which the last desired data ele-
following the last (or last desired) data element from the READ ment is valid, where x equals the CAS latency minus one. This
burst, provided that I/O contention can be avoided. In a given is shown in Figure 11 for each possible CAS latency; data ele-
system design, there may be a possibility that the device ment n+3 is either the last of a burst of four or the last desired
driving the input data will go Low-Z before the SDRAM DQs of a longer burst. Following the PRECHARGE command, a
go High-Z. In this case, at least a single-cycle delay should subsequent command to the same bank cannot be issued until
occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown
in Figures 9 and 10. The DQM signal must be asserted (HIGH)
at least two clocks prior to the write command (DQM latency
is two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs
will go High-Z (or remain High-Z), regardless of the state of
the DQM signal; provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 in Figure 10, the
WRITEs at T5 and T7 would be valid, while the WRITE at T6
would be invalid.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to
ensure that the written data is not masked. Figure 9 shows the
case where the clock frequency allows for bus contention to
be avoided without adding a NOP cycle, and Figure 10 shows
the case where the additional NOP is needed.
tRP is met. Note that part of the row precharge time is hidden
during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge. The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be used
to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts may
be truncated with a BURSTTERMINATE command, provided
that auto precharge was not activated. The BURST TERMI-
NATE command should be issued x cycles before the clock
edge at which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in Figure 12
for each possible CAS latency; data element n+3 is the last
desired data element of a longer burst.
A fixed-length READ burst may be followed by, or trun-
FIGURE 9: READ to WRITE
FIGURE 10: READ to WRITE With
Extra Clock Cycle
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD8M16
Rev. 0.5 04/05
13
AUSTIN [ AUSTIN SEMICONDUCTOR ]
