SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
READ -- FULL-PAGE BURST1
T0
T1
T2
CK
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
t
CL
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
BURST
TERM
NOP
NOP
COMMAND
NOP
NOP
ACTIVE
READ
NOP
NOP
NOP
NOP
t
t
CMS
CMH
DQM /
DQML,
DQMH
t
t
t
t
AS AH
A0-A9,
A11
COLUMN
ROW
2
m
t
AS AH
ROW
A10
BA0, BA1
DQ
t
AS AH
BANK
BANK
t
t
t
t
t
t
t
t
AC
OH
AC
OH
AC
OH
AC
AC
t
t
t
t
OH
AC
OH
OH
DOUT
m
DOUT m+1
DOUTm+2
DOUT m-1
DOUT m
DOUT m+1
t
t
LZ
HZ
t
256 (x16) locations within same row.
Full page completed.
CAS Latency
RCD
Don’t Care
Undefined
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
TIMING PARAMETERS
-8
-10
-8
-10
MIN
MAX
6.5
MIN
MAX
7
SYMBOL*
tAC(3)
UNITS
ns
MIN
1
MAX
MIN
1
MAX
SYMBOL*
tCMH
UNITS
ns
tAC(2)
tAH
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCMS
tHZ(3)
tHZ(2)
tLZ
2
3
ns
ns
ns
ns
ns
ns
1
2
1
3
6
7
8
tAS
10
tCH
3
3.5
3.5
10
15
1
1
1
tCL
3
tOH
2.5
20
2.5
30
tCK(3)
tCK(2)
tCKH
tCKS
8
tRCD
12
1
2
3
* CAS latency indicated in parentheseses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
3. Page left open, no tRP
.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
42
AUSTIN [ AUSTIN SEMICONDUCTOR ]
