SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
ALTERNATING BANK READ ACCESSES1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CL
CLK
CKE
t
t
CK
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND ACTIVE
NOP
NOP
NOP
ACTIVE
READ
NOP
ACTIVE
READ
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AS
AH
A0-A9,
A11
COLUMN b2
ROW
COLUMN m2
ROW
ROW
t
AS
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
ROW
ROW
t
AS
AH
BANK 0
BANK 0
BANK 0
BA0, BA1
DQ
BANK 4
BANK 4
t
t
t
t
t
AC
OH
AC
OH
AC
AC
OH
AC
OH
t
t
t
t
OH
t
t
AC
DOUT
m
DOUT b
DOUT m+1
DOUT m+2
DOUT m+3
t
LZ
CAS Latency - BANK 0
t
t
t
RCD - BANK 0
RCD - BANK 0
RAS - BANK 0
RP - BANK 0
t
t
RC - BANK 0
Don’t Care
Undefined
t
CAS Latency - BANK 1
RRD
RCD - BANK 1
TIMING PARAMETERS
-8
-10
-8
-10
MIN
MAX
6.5
MIN
MAX
MIN
1
MAX
MIN
1
MAX
SYMBOL*
tAC(3)
UNITS
ns
SYMBOL*
tCMH
UNITS
ns
7
9
tAC(2)
tAH
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCMS
tLZ
2
1
3
1
ns
ns
ns
ns
ns
ns
ns
ns
1
2
1
3
tAS
tOH
2.5
50
80
20
24
20
2.5
60
90
30
30
20
tCH
3
3.5
3.5
10
15
1
tRAS
tRC
tRCD
tRP
80,000
80,000
tCL
3
tCK(3)
tCK(2)
tCKH
tCKS
8
12
1
tRRD
2
3
* CAS latency indicated in parentheseses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
41
AUSTIN [ AUSTIN SEMICONDUCTOR ]
