SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
INITIALIZE AND LOAD MODE REGISTER2
T0
T1
Tn+1
t
To+1
Tp+1
Tp+2
Tp+3
t
CK
t
CL
CLK
CH
t
t
CKS CKH
CKE
t
t
t
t
t
t
CMS
CMS
CMS
CMH
CMH
CMH
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
NOP
ACTIVE
NOP
PRECHARGE
NOP NOP
NOP NOP
COMMAND
DQM /
DQML,
DQMH
t
t
t
AH
AS
CODE
t
ROW
ROW
BANK
A0-A9, A11
AS
AH
ALL BANKS
CODE
A10
SINGLE BANK
ALL
BANKS
BA0, BA1
DQ
High-Z
t
t
t
t
MRD
T=100s
RC
RP
RC
Power-up:
VDD and
CLK stable
Precharge
all banks
AUTOREFRESH
AUTOREFRESH
Program Mode Register 1,3,4
Don’t Care
Undefined
TIMING PARAMETERS
-8
-10
-8
-10
MIN
1
MAX
MIN
MAX
SYMBOL*
tCKS
MIN
2
MAX
MIN
3
MAX
UNITS
ns
SYMBOL*
tAH
UNITS
ns
1
3
tCMH
tCMS
tMRD (3)
tRC
tAS
1
2
1
3
ns
ns
2
3
ns
ns
ns
ns
ns
ns
tCH
3.5
3.5
10
15
1
tCK
ns
tCL
2
2
3
tCK (3)
tCK (2)
tCKH
80
24
90
30
8
tRP
ns
12
1
* CAS latency indicated in parentheses.
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care”.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
34
AUSTIN [ AUSTIN SEMICONDUCTOR ]
