SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
POWER-DOWN MODE1
T0
T1
T2
Tn +1
Tn +2
t
t
CK
CL
t
CLK
CKE
t
CH
t
CK
CK
t
t
CKS CKH
t
t
CMS
CMH
NOP
NOP
NOP
ACTIVE
COMMAND PRECHARGE
DQM /
DQML,
DQMH
ROW
ROW
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
t
t
AS AH
BANK(S)
BANK
BA0, BA1
High-Z
DQ
Two clock cycles
Input bufferd gated off while in
power-down mode
All banks idle
Precharge all
active banks
All banks idle, enter
power-down mode
Exit power-down mode
Don’t Care
Undefined
TIMING PARAMETERS
-8
-10
-8
-10
MIN
12
MAX
MIN
15
MAX
MIN
1
MAX
MIN
1
MAX
SYMBOL*
tCK (2)
UNITS
SYMBOL*
tAH
UNITS
ns
ns
ns
ns
ns
ns
tCKH
tCKS
tCMH
tCMS
1
2
1
2
1
3
1
3
tAS
2
3
3
8
3
ns
ns
ns
ns
tCH
3.5
3.5
10
tCL
tCK (3)
* CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down
may result in a loss of data.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
35
AUSTIN [ AUSTIN SEMICONDUCTOR ]
