SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
CLOCK SUSPEND
The clock suspend mode occurs when a column
BURST READ/SINGLEWRITE
The burst read/single write mode is entered by
access/burst is in progress and CKE is registered LOW. In the programming the write burst mode bit (M9) in the Mode
clock suspend mode, the internal clock is deactivated, Register to a logic 1. In this mode, all WRITE commands result
“freezing” the synchronous logic.
in the access of a single column location (burst of one), regard-
For each positive clock edge on which CKE is sampled less of the programmed burst length. READ commands access
LOW, the next internal positive clock edge is suspended. Any columns according to the programmed burst length and
command or data present on the input pins at the time of a sequence, just as in the normal mode of operation (M9=0).
suspended internal clock edge is ignored; any data present on
the DQ pins remains driven; and burst counters are not
incremented, as long as the clock is suspended. (See examples
in Figures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on
the subsequent positive clock edge.
T0
T1
T2
T3
T4
T5
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
CLK
CKE
INTERNAL
CLOCK
INTERNAL
CLOCK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
NOP
WRITE
BANK,
COL n
BANK,
COL n
ADDRESS
DQ
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
n
DQ
DIN
n
DIN
n+1
DIN
n+2
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.
NOTE: For this example, burst length = 4 or greater, and DQM is LOW.
DON’T CARE
Figure 23
Figure 22
CLOCK SUSPEND DURING READ
BURST
CLOCK SUSPEND DURING WRITE
BURST
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
22
AUSTIN [ AUSTIN SEMICONDUCTOR ]
