SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
CONCURRENT AUTO PRECHARGE
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to bank n
will begin when the READ to bank m is registered
(Figure 24).
2. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prir to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin when
the WRITE to bank m is registered (Figure 25).
An access command (READ or WRITE) to another
bank while an access command with AUTO PRECHARGE en-
abled is executing is not allowed by SDRAMs, unless the
SDRAM supports CONCURRENT AUTO PRECHARGE. ASI
SDRAMs support CONCURRENT AUTO PRECHARGE. Four
cases where CONCURRENT AUTO PRECHARGE occurs are
defined below.
T7
T6
T0
T1
T2
T3
T4
T5
CLK
READ-AP
BANK n
READ-AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
Idle
NOP
NOP
BANK n
Internal
States
Page Active
READ with burst of 4
Interrupt Burst, Precharge
tRP-BANK m
tRP - BANK n
Page Active
Precharge
BANK m
READ with burst of 4
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DOUT
a
DOUT a+1
DOUT d+1
DOUT
d
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
Figure 24
READ WITH AUTO PRECHARGE INTERRUPTED BY A READ
T7
T6
T0
T1
T2
T3
T4
T5
CLK
READ-AP
BANK n
WRITE-AP
BANK m
NOP
NOP
COMMAND
NOP
NOP
Idle
NOP
NOP
Page
Active
BANK n
Internal
States
Interrupt Burst, Precharge
READ with burst of 4
tRP - BANK n
tWR-BANKm
Write back
Page Active
BANK m
WRITE with burst of 4
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQM1
D
d+1
D
d+2
D
d+3
IN
IN
IN
DOUT
a
DIN
d
DQ
CAS Latency = 3 (BANK n)
Don’t Care
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
Figure 25
READ WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
23
AUSTIN [ AUSTIN SEMICONDUCTOR ]
