SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
TRUTH TABLE 2-CKE1,2,3,4
CKEn-1
CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
Power-Down
Self Refresh
Clock Suspend
X
X
X
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
L
L
Power-Down
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
5
6
7
L
H
Self Refresh
Exit Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
H
H
L
See Truth Table 3
H
NOTE:
1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n .
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND
INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A
minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next
command at clock edge n + 1.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
25
AUSTIN [ AUSTIN SEMICONDUCTOR ]
