AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
REFRESH
Preserve correct memory cell data by maintaining power and executing a
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
A
/
S refresh cycle
(?R
?
A
/
S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of R
?
AS addresses are executed at least every 32ms, regardless
? /
of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic
?
R
?
A
/
S addressing.
RAS
CAS
ADDR
DQ V IOH
V IOL
,, ,,, ,,,,,, ,,,,, ,,,,,
,
,,
, ,
,
,
,,
V IH
V IL
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
V IH
V IL
WE
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE
The DQs go to High-Z if WE falls, and if
t
WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
Figure 2
?
W
/
E CONTROL OF DQs
,,
,,
,
,,
DON’T CARE
UNDEFINED
AS4LC4M4
Rev. 11/97
DS000022
2-75
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN [ AUSTIN SEMICONDUCTOR ]
