Austin Semiconductor, Inc.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable, as shown
in Figure 4. The burst length determines the maximum number
of column locations that can be accessed for a given READ or
WRITE command.Burst lengths of 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-Ai when the burst length
is set to two, by A2-Ai when the burst length is set to four and
by A3-Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given configuration).
The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. The programmed
burst length applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit M3. The ordering of accesses
within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 2, Burst
Definition.
COTS
COTS PEM
SDRAM
AS4DDR32M16
FIGURE 4: Mode Register Definition
TABLE 2: BURST DEFINITION
STARTING
BURST
COLUMN
LENGTH
ADDRESS
2
A0
0
1
A1 A0
0 0
0 1
1 0
1 1
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
ORDER OF ACCESS
WITHIN A BURST
TYPE =
TYPE =
SEQUENTIAL INTERLEAVED
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
4
NOTES:
1. Whenever a boundary of the block is reached within a given
sequence in Table 2, the following access wraps within the block.
2. For a burst length of two, A1 - Ai select the two-data-element block;
A0 selects the first access within the block.
3. For a burst length of four, A2 - Ai select the four-data-element block;
A0-A1 select the first access within the block.
4. For a burst length of eight, A3 - Ai select the eight-data-element
block; A0-A2 select the first access within the block.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AS4DDR32M16
Rev. 1.5 06/06
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AUSTIN [ AUSTIN SEMICONDUCTOR ]
