Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n-prefetch architecture with
an interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core and two
corresponding
n-bit
wide, one-halfclock-cycle data transfers at
the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR SDRAM during READs and by
the memory controller during WRITEs. DQS is edge-aligned
with data for READs and center-aligned with data for WRITEs.
This offering has two data strobes, one for the lower byte and
one for the upper byte.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK# going
LOW will be referred to as the positive edge of CK. Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as well as to
both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or WRITE
command are used to select the bank and the starting column
location for the burst access.
The DDR SDRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations. An auto precharge
function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All full drive option outputs are
SSTL_2, Class II compatible.
COTS
COTS PEM
SDRAM
AS4DDR32M16
NOTE:
1. The functionality and the timing specifications discussed in
this data sheet are for the DLL-enabled mode of operation.
2. Throughout the data sheet, the various figures and text refer
to DQ’s as “DQ.” The DQ term is to be interpreted as any and all
DQ collectively, unless specifically stated otherwise. Addi-
tionally, the DQ’s are divided into two bytes, the lower byte and
upper byte. For the lower byte (DQ0 through DQ7) DM refers
to LDM and DQS refers to LDQS. For the upper byte (DQ8
through DQ15) DM refers to UDM and DQS refers to UDQS.
3. Complete functionality is described throughout the
document and any page or diagram may have been simplified to
convey a topic and may not be inclusive of all requirements.
4. Any specific requirement takes precedence over a general
statement.
FIGURE 2: 512Mb DDR SRAM Part Number
EXAMPLE: AS4DDR32M16DG-75/IT
-
AS4DDR
32M16
Package
Speed
/
Temperature
TEMPERATURE
Industrial Temperature
Enhanced Temperature
Military Temperature
SPEED
-6
-75
-8
t
CK
= 6ns, CL = 2.5
t
CK
= 7.5ns, CL = 2.5
t
CK
= 8ns, CL = 2.5
PACKAGING
400 mil TSOP
DG
IT
ET
XT
AS4DDR32M16
Rev. 1.5 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN [ AUSTIN SEMICONDUCTOR ]
