Austin Semiconductor, Inc.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, and output drive strength. These
functions are controlled via the bits shown in Figure 6. The
extended mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power. The enabling of
the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW)
to reset the DLL.
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements could result in
unspecified operation.
COTS
COTS PEM
SDRAM
AS4DDR32M16
MODE
FIGURE 6: EXTENDED
REGISTER DEFINITION
OUTPUT DRIVE STRENGTH
The normal drive strength for all outputs are specified to be
SSTL2, Class II. This device supports a programmable option
for reduced drive. This option is intended for the support of the
lighter load and/or point-to-point environments. The selection
of the reduced drive strength will alter the DQ pins and DQS
pins from SSTL2, Class II drive strength to a reduced drive
strength, which is approximately 54 percent of the SSTL2,
Class II drive strength.
NOTES:
1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the Extended
Mode Register vs. the base Mode Register.
2. The reduced drive strength option is supported.
3. The QFC# option is not supported.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-up
initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled, 200
clock cycles must occur before a READ command can be
issued.
AS4DDR32M16
Rev. 1.5 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN [ AUSTIN SEMICONDUCTOR ]
