iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
PRECHARGE COMMAND
FIGURE 13 – PRECHARGE COMMAND
The PREꢁHARGE command, illustrated in Figure 13, is used
to deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row activation a specified time (tRP) after the
PREꢁHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE
command to a different bank is allowed as long as it does
not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Once a bank has
been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that
bank. A PREꢁHARGE command is allowed if there is no
open row in that bank (idle state) or if the previously open
row is already in the process of precharging. However, the
precharge period will be determined by the last PREꢁHARGE
command issued to the bank.
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
ADDRESS
A10
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA1–BA0 select the bank. Otherwise
BA1–BA0 are treated as “Don’t ꢁare.” When all banks are to
be precharged, inputs BA1–BA0 are treated as “Don’t ꢁare.”
ALL BANKS
ONE BANK
BA
BA0, BA1
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. tRPA timing applies when the
PREꢁHARGE (ALL) command is issued, regardless of the
number of banks already open or closed. If a single-bank
PREꢁHARGE command is issued, tRP timing applies.
DON’T CARE
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
issued). The differential clock should remain stable and meet
tꢁKE specifications at least 1 x tꢁK after entering self refresh
mode. All command and address input signals except ꢁKE are
“Don’t ꢁare” during self refresh.
SELF REFRESH COMMAND
The SELF REFRESH command can be used to retain data
in the DDR2 SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR2 SDRAM
retains data without external clocking. All power supply
inputs (including VREF) must be maintained at valid levels
upon entryꢀexit and during SELF REFRESH operation.
The procedure for exiting self refresh requires a sequence of
commands. First, the differential clock must be stable and meet
tꢁK specifications at least 1 x tꢁK prior to ꢁKE going back
HIGH. Once ꢁKE is HIGH (tꢁLE(MIN) has been satisfied with
four clock registrations), the DDR2 SDRAM must have NOP or
DESELEꢁT commands issued for tXSNR because time is
required for the completion of any internal refresh in progress.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOP or DESELEꢁT commands for
200 clock cycles before applying any other command.
The SELF REFRESH command is initiated like a REFRESH
command except ꢁKE is LOW. The DLL is automatically
disabled upon entering self refresh and is automatically
enabled upon exiting self refresh (200 clock cycles must
then occur before
a
READ command can be
Note: Self refresh not available at military temperature.
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
20
AUSTIN [ AUSTIN SEMICONDUCTOR ]
