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AS28F128J3MRG-15/XT 参数 Datasheet PDF下载

AS28F128J3MRG-15/XT图片预览
型号: AS28F128J3MRG-15/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 塑封微电路128MB, x8和x16 Q- FLASH内存,即使扇形,每个单元架构单位 [Plastic Encapsulated Microcircuit 128Mb, x8 and x16 Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture]
分类和应用: 内存集成电路光电二极管
文件页数/大小: 8 页 / 112 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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PEM  
AS28F128J3M  
Q-Flash  
Austin Semiconductor, Inc.  
AC Switching Characteristics:  
(VDD=3.0V –5%/+10%, TA= Min. / Max. temperatures of  
Operational Range chosen)  
Symbol  
128Mb  
Parameter  
Units  
Notes  
Write Operations  
Min  
1.0  
0
70.0  
50.0  
55.0  
0
Max  
RP\ High Recovery to WE\ (CEx) going Low  
CEx (WE\) Low to WE\ (CEx) going High  
Write Pulse Width  
Data Setup to WE\ going High  
Address Setup to WE\ going High  
CEx Hold from WE\ High  
tRS  
tCS  
tWP  
tDS  
tAS  
tCH  
us  
ns  
ns  
ns  
us  
ns  
1
Data Hold from WE\ High  
tDH  
0
Address Hold from WE\ High  
Write Pulse Width High  
tAH  
0
30  
0
tWPH  
tVPS  
tWR  
tSTS  
tVPH  
tWB  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
VPEN Setup to WE\ going High  
Write Recovery before READ  
WE\ High to STA going Low  
VPEN Hold from valid SRD, STS going High  
WE\ High to Status Registry Busy  
1
35  
200  
200  
0
1
1
Block Erase, Program and Lock Bit Performance  
Write Buffer Byte Program time (Program time 32 Bytes/ 16 Words)  
Byte/Word Program time  
Block Program time  
Block Erase time  
Set Lock Bits time  
Clear Block Lock Bits time  
Program Suspend Latency time to Read  
Erase Suspend Latency time to Read  
Typ  
180  
Max  
654  
630  
1.70  
5
75  
0.70  
30  
tWED1  
tWED2  
tWED3  
tWED4  
tWED5  
tWED6  
tLPS  
us  
us  
sec  
sec  
us  
sec  
us  
us  
11.20  
0.70  
0.75  
10.00  
0.50  
25  
tLES  
25  
35  
Read Only Operations  
Read Cycle time  
Address to Output Delay  
CEx to Output Delay  
OE\ to Non-Array Output Delay  
OE\ to Array Output Delay  
RP\ High to Output Delay  
CEx to Output in Low-Z  
Min  
115  
Max  
tRC  
tAA  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
115  
115  
50  
25  
210  
tACE  
tAOE  
tAOA  
tRWH  
tOEC  
tOEO  
tODC  
tODO  
tOH  
0
0
1
1
1
1
1
OE\ to Output in Low-Z  
Cex High to Output in High-Z  
OE\ High to Output in High-Z  
Output Hold from Address, Cex, or OE\ change,  
whichever occurs first  
35  
15  
0
CEx Low to BYTE\ High or Low  
BYTE\ to Output Delay  
BYTE\ to Output in High-Z  
CEx High to CEx Low  
tCB  
tABY  
tODB  
tCWH  
tAPA  
10  
1,000  
1,000  
ns  
ns  
ns  
ns  
ns  
1
1
1
1
0.0  
Page Address Access  
25  
Reset Specifications  
RP\ Pulse Low time  
RP\ High to RESET during BLOCK ERASE, PROGRAM, or  
Lock Bit configuration  
Min  
35  
Max  
100  
tPLPH  
tPHRH  
us  
ns  
Notes to Switching Specifications:  
1.  
Sampled, not 100% tested  
AS28F128J3MRG  
Revision 5.0 11/23/04  
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification  
For Additional Products and Information visit out Web site at www.austinsemiconductor.com  
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