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AS28F128J3MRG-15/XT 参数 Datasheet PDF下载

AS28F128J3MRG-15/XT图片预览
型号: AS28F128J3MRG-15/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 塑封微电路128MB, x8和x16 Q- FLASH内存,即使扇形,每个单元架构单位 [Plastic Encapsulated Microcircuit 128Mb, x8 and x16 Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture]
分类和应用: 内存集成电路光电二极管
文件页数/大小: 8 页 / 112 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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PEM  
AS28F128J3M  
Q-Flash  
Austin Semiconductor, Inc.  
Three Chip Enable (CEx) pins are used for enabling and disabling  
the device by activating the device’s control logic, input buffer,  
decoders, and sense amplifiers.  
Chip Enable Truth Table  
CE2  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIH  
CE1  
VIL  
VIL  
VIH  
VIH  
VIL  
VIL  
VIH  
VIH  
CE0  
VIL  
VIH  
VIL  
VIH  
VIL  
VIH  
VIL  
VIH  
Device  
Enabled  
Disabled  
Disabled  
Disabled  
Enabled  
Enabled  
Enabled  
Disabled  
BYTE\ enables the device to be used in x8 or x16 configuration.  
Byte=Low (logic 0) selects and 8-bit mode with address zero (A0)  
selecting the High or Low Byte and Byte=High (logic 1) selects  
the 16-bit or Word mode. When the device is in Word mode,  
address one (A1) becomes the low order address bit and address  
zero (A0) becomes a no-connect (NC).  
RP\ is used to reset the device. When the device is disabled and  
RP\ is at VCC, the STANDBY mode is enabled. A reset time  
(tRWH) is required after RP\ switches to a High (logic 1) and the  
outputs become valid. Likewise, the device has a wake time (tRS)  
from RP\ High until WRITES to the Command User Interface  
[CUI] are recognized, RESETS the ISM and clears the status  
register.  
Absolute Maximum Ratings  
Voltage  
Min  
Max  
Units  
0C  
Notes  
Temperature under  
-55  
125  
Capacitance  
Parameter/Condition  
Bias  
0C  
V
Symbol  
Typ  
Max  
Units  
Storage Temperature  
For VCCQ=2.7v to 3.6v  
Voltage on any pin  
Short Circuit Current  
-65  
-2  
125  
5
Input Capacitance  
Output Capacitance  
Cin  
Cbyte  
Cout  
5
14  
5
8
16  
12  
pF  
pF  
pF  
100  
mA  
1
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions greater than those  
indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum conditions for any duration or segment of time may affect  
device reliability.  
Notes  
1: All specified voltages are with respect to GND. Minimum DC  
voltage is -0.5v on input/output pins and -0.2v on Vcc and VPEN  
pins. During transitions, this level may undershoot to -2.0v for  
periods </= 20ns. Maximum DC voltage on input/output pins,  
Vcc and VPEN is VCC+0.5V which, during transitions, may  
overshoot to Vcc + 2.0v for periods <20ns.  
Pin Description Table:  
Signal Name  
Symbol  
Type  
Input  
Pin  
Description  
Address  
A0, A1, A2. A3,  
A4, A5, A6, A7  
A8, A9, A10, A11  
A12,A13,A14,A15  
A16,A17,A18,A19  
A20,A21,A22,A23  
CE0, CE1, CE2  
WE\  
32,28,27,26,  
25,24,23,22,  
20,19,18,17,  
13,12,11,10,  
8,7,6,5,  
4,3,1,30  
14,2,29  
55  
Address Inputs during READ and WRITE Operations. A0 is only  
used in x8 mode and will be a NC in x16 mode.  
Chip Enables  
Write Enable  
Reset/Power-Down  
Input  
Input  
Input  
Three Chip Enable pins for Multiple devices. See chart for function  
Write Control  
Reset/Power-Down, When Low the control pin resets the status Reg.  
and ISM to array READ mode.  
RP\  
16  
Output Enable  
OE\  
Input  
Input  
Input  
54  
31  
15  
Ouput Enable control enable data output buffers when Low, and when  
High the output buffers are disabled  
Configuration Control pin. When High the device is in x16 mode, when  
Low the device is in Byte mode (x8)  
Necessary Voltage pin for Programming, Erasing or configuring lock  
bits. Typically connected to VCC. When VPEN</=VPENLK, this  
enables Hardware Write Protect.  
Byte Mode Control  
Programming Voltage  
BYTE\  
VPEN  
Status Pin/Flag  
STS  
Output  
Supply  
53  
43  
Indicates the status of the ISM. When configured in level mode, STS  
acts as a RY/BY\ pin. When configured in its pulse mode, it can  
pulse to indicate PROGRAM and or ERASE completion.  
Separate/Isolated Voltage supply for Input/Output bus. Allows  
voltage matching to different interface standards.  
Input/Output Voltage  
VCCQ  
Supply Voltage  
Digital Ground  
No Connect(s)  
VCC  
GND  
NC  
Supply  
Supply  
-
9, 37  
21, 42, 48  
1, 30, 56  
Power Supply: 2.7V - 3.6V  
Ground  
No electrical connection or function  
AS28F128J3MRG  
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification  
Revision 5.0 11/23/04  
For Additional Products and Information visit out Web site at www.austinsemiconductor.com  
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