PEM
AS28F128J3M
Q-Flash
Austin Semiconductor, Inc.
Memory Command Set Operations:
Scalable or Basic Command
First Bus Cycle
Address
Second Bus Cycle
Bus Cycles Operation
Data
Operation
Address
Data
Notes
Command
READ ARRAY
READ IDENTIFIER CODES
Set [SCS or BCS]
SCS / BCS
SCS / BCS
1
WRITE
WRITE
X
X
FFh
90h
>/= 2
READ
IA
ID
1
READ QUERY
READ STATUS REGISTER
SCS
SCS / BCS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
X
X
98h
70h
READ
READ
QA
X
QD
SRD
2
2
1
CLEAR STATUS REGISTER
WRITE TO BUFFER
WORD/BYTE PROGRAM
BLOCK ERASE
BLOCK ERASE/PROGRAM
SUSPEND
SCS / BCS
SCS / BCS
X
BA
50h
E8h
WRITE
WRITE
WRITE
BA
PA
BA
N
3, 4, 5
6, 7
5, 6
>2
2
2
SCS / BCS
SCS / BCS
SCS / BCS
X
BA
X
40h or 10h
20h
PD
D0h
1
B0h
7, 8
BLOCK ERASE/PROGRAM
RESUME
SCS / BCS
1
WRITE
X
D0h
7
CONFIGURATION
SCS
SCS
SCS
2
2
2
2
WRITE
WRITE
WRITE
WRITE
X
X
X
X
B8h
60h
60h
C0h
WRITE
WRITE
WRITE
WRITE
X
BA
X
CC
01h
D0h
PD
SET BLOCK LOCK BITS
CLEAR BLOCK LOCK BITS
PROTECTION PROGRAM
PA
Key:
[IA]
[ID]
Identifier Code address
Data read from identifier Code
Address within a Block
[BA]
[QA]
[PA]
Query data base Address
Address of Memory location to be programmed
[QD]
[SRD]
Data read from Query data base
Data read from Status Register
Notes
[1]
[2]
Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.
If the ISM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 are placed in High-Z
[3]
[4]
After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for WRITING
The number of Bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. Count ranges on this device
for byte mode are n=00H to n=1Fh and for word mode, n=0000h to 000Fh. The third and consecutive bus cycles, as determined by n,
are for writing data into the write buffer. The CONFIRM command (D0h) is expected after exactly n+1 WRITE cycles; any other
command at that point in the sequence aborts the WRITE-to-BUFFER operation.
[5]
[6]
[7]
[8]
The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued
Attempts to issue a BLOCK ERASE or PROGRAM to a locked block will fail
Etiher 40h or 10h is recognized by the ISM as the byte/word program setup
PROGRAM SUSPEND can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is inititated.
The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.
AS28F128J3MRG
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 5.0 11/23/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
5
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