Electrical Characteristics
All parameters refer to GND, Tamb = -40LC to +105LC, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5 V, Tamb = 25LC)
6.76438 MHz Osc.
(MODE: 1)
4.90625 MHz Osc.
(MODE: 0)
Variable Oscillator
Min. Typ. Max.
Parameter
Test Conditions
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Basic Clock Cycle of the Digital Circuitry
Basic clock
cycle
MODE = 0 (USA)
MODE = 1 (Europe)
1/fXTO/10
1/fXTO/14
1/fXTO/10
1/fXTO/14
µs
µs
TClk
2.0383
2.0383
2.0697
2.0697
Extended basic BR_Range0
16.6
8.3
4.1
2.1
16.6
8.3
4.1
16.3
8.2
4.1
2.0
16.3
8.2
4.1
8 PꢀTClk
4ꢀPꢀTClk
2 PꢀTClk
1 PꢀTClk
8 PꢀTClk
4ꢀPꢀTClk
2 PꢀTClk
1 PꢀTClk
µs
µs
µs
µs
clock cycle
BR_Range1
BR_Range2
BR_Range3
TXClk
2.1
2.0
Polling Mode
Sleep time (see Sleep and XSleep
Figure 10, are defined in the
Figure 19, and OPMODE register
Figure 33)
Sleep Pꢀ
Sleep Pꢀ Sleep Pꢀ
Sleep Pꢀ Sleep Pꢀ
1024 Pꢀ 1024 Pꢀ
Sleep Pꢀ
XSleep Pꢀ
1024 Pꢀ
2.0383
Sleep Pꢀ
Sleep Pꢀ
X
Sleep Pꢀ
X
X
TSleep
XSleep Pꢀ
XSleep Pꢀ
ms
1024 Pꢀ
2.0697
1024 PꢀTClk
1024 PꢀTClk
2.0697 2.0383
Start-up time
BR_Range0
1855
1061
1061
663
1855
1061
1061
663
1827
1045
1045
653
1827
1045
1045
653
896.5
512.5
512.5
896.5
512.5
512.5
320.5 Pꢀ
TClk
µs
µs
µs
µs
(see Figure 10, BR_Range1
and Figure 11) BR_Range2
BR_Range3
TStartup
320.5ꢀPꢀTClk
Time for bit
check (see
Figure 10)
Average bit-check
time while polling,
no RF applied
(see Figure 14, and
Figure 15)
ms
ms
ms
ms
BR_Range0
BR_Range1
BR_Range2
BR_Range3
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
TBit-check
Bit-check time for a
valid input signal fSig ,
(see Figure 11)
NBit-check = 0
1 X TXClk
3/fSig
6/fSig
1 PꢀTClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
TBit-check
NBit-check = 3
3/fSig
6/fSig
9/fSig
3.5/fSig
6.5/fSig
9.5/fSig
3/fSig
6/fSig
9/fSig
3.5/fSig
6.5/fSig
9.5/fSig
N
Bit-check = 6
NBit-check = 9
9/fSig
Receiving Mode
Intermediate
frequency
MODE = 0 (USA)
MODE = 1 (Europe)
f
XTO Pꢀ64/314
MHz
MHz
fIF
1.0
1.0
fXTO Pꢀ64/432.92
Baud-rate
range
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
1.8
3.2
5.6
1.8
3.2
5.6
1.0
1.8
3.2
5.6
1.8
3.2
5.6
BR_Range0 Pꢀ2 ꢁs/TClk
BR_Range1 Pꢀ2 ꢁs/TClk
BR_Range2 Pꢀ2 ꢁs/TClk
BR_Range3 Pꢀ2 ꢁs/TClk
kBaud
kBaud
kBaud
kBaud
BR_Range
10.0
10.0
Minimum time
period between
edges at Pin
DATA
(see Figure 7,
Figure 17 and
Figure 18, with
the exception of
parameter
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
165
83
41.4
20.7
165
83
41.4
20.7
163
81
40.7
20.4
163
81
40.7
20.4
10 PꢀTXClk
10 PꢀTXClk
10 PꢀTXClk
10 PꢀTXClk
10 PꢀTXClk
µs
µs
µs
µs
tDATA-min
10 PꢀTXClk
10 PꢀTXClk
10 PꢀTXClk
TPulse
)
32
T5743
4569A–RKE–12/02
ATMEL [ ATMEL ]
