ATmega64A
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn } = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01)
or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully
acceptable, as a high-impedant environment will not notice the difference between a strong high
driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to
one to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state({DDxn,
PORTxn} = 0b11) as an intermediate step.
Table 13-1 summarizes the control signals for the pin value.
Table 13-1. Port Pin Configurations
PUD
DDxn
PORTxn
(in SFIOR)
I/O
Pull-up
No
Comment
0
0
0
1
1
0
1
1
0
1
X
0
Input
Tri-state (Hi-Z)
Input
Yes
No
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
1
Input
X
X
Output
Output
No
Output Low (Sink)
Output High (Source)
No
13.2.2
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 13-2, the PINxn Register bit and the preceding latch con-
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay. Figure 13-3 shows a timing dia-
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted tpd,max and tpd,min respectively.
70
8160C–AVR–07/09
ATMEL [ ATMEL ]
