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ATMEGA64A-AU 参数 Datasheet PDF下载

ATMEGA64A-AU图片预览
型号: ATMEGA64A-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有64K字节的系统内可编程闪存 [8-bit Microcontroller with 64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 7964 K
品牌: ATMEL [ ATMEL ]
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ATmega64A  
values are read back again, but as previously discussed, a nop instruction is included to be able  
to read back the value recently assigned to some of the pins.  
Assembly Code Example(1)  
:.  
; Define pull-ups and set outputs high  
; Define directions for port pins  
ldi  
ldi  
out  
out  
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)  
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)  
PORTB,r16  
DDRB,r17  
; Insert nop for synchronization  
nop  
; Read port pins  
in  
:.  
r16,PINB  
C Code Example  
unsigned char i;  
:.  
/* Define pull-ups and set outputs high */  
/* Define directions for port pins */  
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);  
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);  
/* Insert nop for synchronization*/  
_NOP();  
/* Read port pins */  
i = PINB;  
:.  
Note:  
1. For the assembly program, two temporary registers are used to minimize the time from pull-  
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3  
as low and redefining bits 0 and 1 as strong high drivers.  
13.2.3  
Digital Input Enable and Sleep Modes  
As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the  
Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in  
Power-down mode, Power-save mode, Standby mode, and Extended Standby mode to avoid  
high power consumption if some input signals are left floating, or have an analog signal level  
close to VCC/2.  
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt  
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various  
other alternate functions as described in “Alternate Port Functions” on page 73.  
If a logic high level (“one”) is present on an asynchronous External Interrupt pin configured as  
“Interrupt on Any Logic Change on Pin” while the External Interrupt is not enabled, the corre-  
sponding External Interrupt Flag will be set when resuming from the above mentioned sleep  
modes, as the clamping in these sleep modes produces the requested logic change.  
72  
8160C–AVR–07/09  
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