ATmega64A
Figure 10-1. Reset Logic
DATA BUS
D
Q
Q
MCU Control and Status
Register (MCUCSR)
PEN
L
Pull-up Resistor
Power-On Reset
Circuit
Brown-Out
Reset Circuit
BODEN
BODLEVEL
Pull-up Resistor
SPIKE
FILTER
Reset Circuit
RESET
JTAG Reset
Register
Watchdog
Timer
Watchdog
Oscillator
Delay Counters
Clock
CK
TIMEOUT
Generator
CKSEL[3:0]
SUT[1:0]
10.0.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detection level
is defined in Table 28-3. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
52
8160C–AVR–07/09
ATMEL [ ATMEL ]
