ATmega64A
9.8
Register Description
9.8.1
MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
Bit
7
6
SRW10
R/W
0
5
SE
R/W
0
4
3
2
1
0
0x35 (0x55)
Read/Write
Initial Value
SRE
R/W
0
SM1
R/W
0
SM0
R/W
0
SM2
R/W
0
IVSEL
R/W
0
IVCE
R/W
0
MCUCR
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bits 4:2 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the six available sleep modes as shown in Table 9-2.
Table 9-2.
Sleep Mode Select
SM2
SM1
SM0
0
Sleep Mode
Idle
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
ADC Noise Reduction
Power-down
Power-save
Reserved
0
1
0
1
Reserved
0
Standby(1)
1
Extended Standby(1)
Note:
1. Standby mode and Extended Standby mode are only available with external crystals or
resonators.
50
8160C–AVR–07/09
ATMEL [ ATMEL ]
