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ATMEGA64A-AU 参数 Datasheet PDF下载

ATMEGA64A-AU图片预览
型号: ATMEGA64A-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有64K字节的系统内可编程闪存 [8-bit Microcontroller with 64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 7964 K
品牌: ATMEL [ ATMEL ]
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ATmega64A  
9.3  
Power-down Mode  
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-  
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the  
Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).  
Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface  
address match interrupt, an external level interrupt on INT7:4, or an External Interrupt on INT3:0  
can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation  
of asynchronous modules only.  
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed  
level must be held for some time to wake up the MCU. Refer to “8-bit Timer/Counter0 with PWM  
and Asynchronous Operation” on page 92 for details.  
When waking up from Power-down mode, there is a delay from the wake-up condition occurs  
until the wake-up becomes effective. This allows the clock to restart and become stable after  
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the  
Reset Time-out period, as described in “Clock Sources” on page 38.  
9.4  
Power-save Mode  
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-  
save mode. This mode is identical to Power-down, with one exception:  
If Timer/Counter0 is clocked asynchronously (i.e., the AS0 bit in ASSR is set), Timer/Counter0  
will run during sleep. The device can wake up from either Timer Overflow or Output Compare  
event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in  
TIMSK, and the Global Interrupt Enable bit in SREG is set.  
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended  
instead of Power-save mode because the contents of the registers in the asynchronous timer  
should be considered undefined after wake-up in Power-save mode if AS0 is 0.  
This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous  
modules, including Timer/Counter0 if clocked asynchronously.  
9.5  
9.6  
Standby Mode  
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the  
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down  
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up  
in six clock cycles.  
Extended Standby Mode  
When the SM2:0 bits are 111 and an external crystal/resonator clock option is selected, the  
SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to  
Power-save mode with the exception that the Oscillator is kept running. From Extended Standby  
mode, the device wakes up in six clock cycles.  
47  
8160C–AVR–07/09  
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