ATmega64A
Table 25-7. ATmega64A Boundary-scan Order (Continued)
Bit Number
103
102
101
100
99
Signal Name
RSTT
Module
Reset Logic
(Observe-only)
RSTHV
EXTCLKEN
OSCON
Enable Signals for Main Clock/Oscillators
RCOSCEN
98
OSC32EN
97
EXTCLK (XTAL1)
OSCCK
Clock Input and Oscillators for the Main Clock
(Observe-only)
96
95
RCCK
94
OSC32CK
93
TWIEN
TWI
92
PD0.Data
Port D
91
PD0.Control
PD0.Pullup_Enable
PD1.Data
90
89
88
PD1.Control
PD1.Pullup_Enable
PD2.Data
87
86
85
PD2.Control
PD2.Pullup_Enable
PD3.Data
84
83
82
PD3.Control
PD3.Pullup_Enable
PD4.Data
81
80
79
PD4.Control
PD4.Pullup_Enable
PD5.Data
78
77
76
PD5.Control
PD5.Pullup_Enable
PD6.Data
75
74
73
PD6.Control
PD6.Pullup_Enable
PD7.Data
72
71
70
PD7.Control
PD7.Pullup_Enable
PG0.Data
69
68
Port G
277
8160C–AVR–07/09
ATMEL [ ATMEL ]
