ATmega64A
Figure 25-5. Additional Scan Signal for the Two-wire Interface
PUExn
OCxn
ODxn
TWIEN
Pxn
SRC
Slew-rate limited
IDxn
25.5.3
Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 25-6 is
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 25-6. Observe-only Cell
To
Next
ShiftDR
Cell
FF1
0
1
D
Q
From
ClockDR
Previous
Cell
265
8160C–AVR–07/09