ATmega64A
Figure 25-4. General Port Pin Schematic Diagram
See Boundary-scan Description
for Details!
PUExn
PUD
WDx
Q
D
DDxn
Q CLR
RESET
OCxn
RDx
Q
D
Pxn
PORTxn
ODxn
Q CLR
WPx
RRx
IDxn
RESET
SLEEP
SYNCHRONIZER
RPx
D
Q
D
L
Q
Q
PINxn
Q
CLK I/O
PUD:
PULLUP DISABLE
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
PUExn:
OCxn:
ODxn:
IDxn:
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
SLEEP:
CLK I/O
:
25.5.2
Boundary-scan and the Two-wire Interface
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in Figure 25-5, the TWIEN signal enables
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in Figure 25-9 is attached to the TWIEN signal.
Note:
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
drive contention.
264
8160C–AVR–07/09
ATMEL [ ATMEL ]
