ATmega64A
21. TWI – Two-wire Serial Interface
21.1 Features
• Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up when AVR is in Sleep Mode
21.2 Overview
The TWI module is comprised of several submodules, as shown in Figure 21-1. All registers
drawn in a thick line are accessible through the AVR data bus.
Figure 21-1. Overview of the TWI Module
SCL
SDA
Spike
Filter
Spike
Filter
Slew-rate
Control
Slew-rate
Control
Bus Interface Unit
Bit Rate Generator
START / STOP
Spike Suppression
Prescaler
Control
Address/Data Shift
Register (TWDR)
Bit Rate Register
(TWBR)
Arbitration Detection
Ack
Address Match Unit
Control Unit
Address Register
(TWAR)
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status Control
Address Comparator
201
8160C–AVR–07/09
ATMEL [ ATMEL ]
