ATmega64A
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero)
will not become effective until ongoing and pending transmissions are completed, i.e., when the
Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
When disabled, the Transmitter will no longer override the TxD port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRC sets the number of data bits
(Character Size) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
20.11.4 UCSRnC – USART Control and Status Register C(1)
Bit
7
6
5
4
3
USBSn
R/W
0
2
UCSZn1
R/W
1
UCSZn0
R/W
0
UCPOLn
R/W
–
UMSELn
UPMn1
UPMn0
R/W
0
UCSRnC
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
1
1
0
Note:
1. This register is not available in ATmega103 compatibility mode.
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this bit must be written to
zero when UCSRC is written.
• Bit 6 – UMSELn: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 20-8. UMSEL Bit Settings
UMSELn
Mode
0
1
Asynchronous Operation
Synchronous Operation
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
198
8160C–AVR–07/09
ATMEL [ ATMEL ]
