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ATMEGA64A-AU 参数 Datasheet PDF下载

ATMEGA64A-AU图片预览
型号: ATMEGA64A-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有64K字节的系统内可编程闪存 [8-bit Microcontroller with 64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 7964 K
品牌: ATMEL [ ATMEL ]
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ATmega64A  
21.4.2  
START and STOP Conditions  
The Master initiates and terminates a data transmission. The transmission is initiated when the  
Master issues a START condition on the bus, and it is terminated when the Master issues a  
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no  
other Master should try to seize control of the bus. A special case occurs when a new START  
condition is issued between a START and STOP condition. This is referred to as a REPEATED  
START condition, and is used when the Master wishes to initiate a new transfer without relin-  
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next  
STOP. This is identical to the START behavior, and therefore START is used to describe both  
START and REPEATED START for the remainder of this data sheet, unless otherwise noted.  
As depicted below, START and STOP conditions are signalled by changing the level of the SDA  
line when the SCL line is high.  
Figure 21-4. START, REPEATED START, and STOP Conditions  
SDA  
SCL  
START  
STOP START  
REPEATED START  
STOP  
21.4.3  
Address Packet Format  
All address packets transmitted on the TWI bus are nine bits long, consisting of seven address  
bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read  
operation is to be performed, otherwise a write operation should be performed. When a slave  
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL  
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-  
ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then  
transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An  
address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or  
SLA+W, respectively.  
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the  
designer, but the address 0000 000 is reserved for a general call.  
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK  
cycle. A general call is used when a Master wishes to transmit the same message to several  
slaves in the system. When the general call address followed by a write bit is transmitted on the  
bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.  
The following data packets will then be received by all the slaves that acknowledged the general  
call. Note that transmitting the general call address followed by a Read bit is meaningless, as  
this would cause contention if several slaves started transmitting different data.  
All addresses of the format 1111 xxx should be reserved for future purposes.  
205  
8160C–AVR–07/09  
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