16.10.10 CAN Bit Timing Register 3 - CANBT3
Bit
7
-
6
PHS22
R/W
0
5
PHS21
R/W
0
4
PHS20
R/W
0
3
PHS12
R/W
0
2
PHS11
R/W
0
1
PHS10
R/W
0
0
SMP
R/W
0
CANBT3
Read/Write
Initial Value
-
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT3 is written.
• Bit 6:4 – PHS22:0: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f. Section 16.2.3
“CAN Bit Timing” on page 170 and Section 16.4.3 “Baud Rate” on page 177).
Tphs2 = Tscl x (PHS2 [2:0] + 1)
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
Tphs1 = Tscl x (PHS1 [2:0] + 1)
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
– 0 - the sampling will occur once at the user configured sampling point - SP.
– 1 - with three-point sampling configuration the first sampling will occur two TclkIO
clocks before the user configured sampling point - SP, again at one TclkIO clock
before SP and finally at SP. Then the bit level will be determined by a majority vote of
the three samples.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ = TclkIO.
If BRP = 0, SMP must be cleared.
16.10.11 CAN Timer Control Register - CANTCON
Bit
7
6
5
TPRSC5
R/W
4
TPRSC4
R/W
3
TPRSC3
R/W
2
TPRSC2
R/W
1
TRPSC1
R/W
0
TPRSC0
R/W
TPRSC7
R/W
TPRSC6
R/W
CANTCON
Read/Write
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
TclkCANTIM = TclkIO x 8 x (CANTCON [7:0] + 1)
194
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
