16.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1
Bit
7
-
6
-
5
4
3
2
1
0
IEMOB5
IEMOB4
IEMOB3
IEMOB2
IEMOB1
IEMOB0
CANIE2
CANIE1
-
-
-
13
R/W
0
-
12
R/W
0
-
11
R/W
0
-
10
R/W
0
-
9
-
8
Bit
15
R/W
0
14
R/W
0
Read/Write
Initial Value
Read/Write
Initial Value
R/W
0
R/W
0
R
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
• Bits 5:0 - IEMOB5:0: Interrupt Enable by MOb
– 0 - interrupt disabled.
– 1 - MOb interrupt enabled
Note:
Example: CANIE2 = 0000 1100b : enable of interrupts on MOb 2 & 3.
• Bit 15:6 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, it must be written to
zero when CANIE1 & CANIE2 are written.
16.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
Bit
7
6
5
4
3
SIT3
-
2
SIT2
-
1
SIT1
-
0
SIT0
-
-
-
SIT5
SIT4
CANSIT2
CANSIT1
-
15
R
0
-
14
R
0
-
13
R
0
-
12
R
0
Bit
11
R
10
R
9
8
Read/Write
Initial Value
Read/Write
Initial Value
R
R
0
0
0
0
R
0
R
0
R
0
R
0
R
R
R
R
0
0
0
0
• Bits 5:0 - SIT5:0: Status of Interrupt by MOb
– 0 - no interrupt.
– 1- MOb interrupt.
Note:
Example: CANSIT2 = 0010 0001b : MOb 0 & 5 interrupts.
• Bit 15:6 – Reserved Bits
These bits are reserved for future use.
16.10.8 CAN Bit Timing Register 1 - CANBT1
Bit
7
6
BRP5
R/W
0
5
BRP4
R/W
0
4
BRP3
R/W
0
3
BRP2
R/W
0
2
BRP1
R/W
0
1
BRP0
R/W
0
0
-
-
-
-
CANBT1
Read/Write
Initial Value
-
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
192
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
