ATmega16/32/64/M1/C1
14.16.3 PSC Output Compare SA Register – POCRnSAH and POCRnSAL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnSA[11:8]
POCRnSAH
POCRnSAL
POCRnSA[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.4 PSC Output Compare RA Register – POCRnRAH and POCRnRAL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnRA[11:8]
POCRnRAH
POCRnRAL
POCRnRA[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.5 PSCOutput Compare SB Register – POCRnSBH and POCRnSBL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnSB[11:8]
POCRnSBH
OCRnSBL
POCRnSB[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.6 PSC Output Compare RB Register – POCR_RBH and POCR_RBL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnRB[11:8]
POCR_RBH
POCR_RBL
POCRnRB[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note:
n = 0 to 2 according to module number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSC counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers.
14.16.7 PSC Configuration Register – PCNF
Bit
7
6
5
PULOCK
R/W
4
PMODE
R/W
0
3
POPB
R/W
0
2
POPA
R/W
0
1
-
0
-
-
-
PCNF
Read/Write
Initial Value
R
0
R
0
R
0
R
0
0
• Bit 7:6 - not use
not use
• Bit 5 – PULOCK: PSC Update Lock
When this bit is set, the Output Compare Registers POCRnRA, POCRnSA, POCRnSB,
POCR_RB and the PSC Output Configuration Registers POC can be written without disturbing
the PSC cycles. The update of the PSC internal registers will be done if the PULOCK bit is
released to zero.
153
7647F–AVR–04/09
ATMEL [ ATMEL ]
