Table 14-12. Input Mode Operation
PRFMn2:0
000b
Description
No action, PSC Input is ignored
Disactivate module n Outputs A
Disactivate module n Output B
Disactivate module n Output A & B
Disactivate all PSC Output
001b
010b
011b
10x
11xb
Halt PSC and Wait for Software Action
14.16.10 PSC Interrupt Mask Register – PIM
Bit
7
-
6
-
5
-
4
-
3
PEVE2
R/W
0
2
PEVE1
R/W
0
1
PEVE0
R/W
0
0
PEOPE
R/W
0
PIM
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7:4 – not use
not use.
• Bit 3 – PEVE2 : PSC External Event 2 Interrupt Enable
When this bit is set, an external event which can generates a a fault on module 2 generates also
an interrupt.
• Bit 2 – PEVE1 : PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also
an interrupt.
• Bit 1 – PEVE0 : PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also
an interrupt.
• Bit 0 – PEOPE : PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
156
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
