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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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Table 26-11. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-  
pointer, ATmega168  
Corresponding  
Variable  
Z-value(1)  
Description  
Most significant bit in the Program Counter. (The  
Program Counter is 12 bits PC[11:0])  
PCMSB  
12  
5
Most significant bit which is used to address  
the words within one page (64 words in a page  
requires 6 bits PC [5:0])  
PAGEMSB  
ZPCMSB  
Bit in Z-register that is mapped to PCMSB. Because  
Z0 is not used, the ZPCMSB equals PCMSB + 1.  
Z13  
Z6  
Bit in Z-register that is mapped to PAGEMSB.  
Because Z0 is not used, the ZPAGEMSB equals  
PAGEMSB + 1.  
ZPAGEMSB  
PCPAGE  
Program counter page address: Page select, for  
page erase and page write  
PC[12:6]  
PC[5:0]  
Z13:Z7  
Z6:Z1  
Program counter word address: Word select, for  
filling temporary buffer (must be zero during page  
write operation)  
PCWORD  
Note:  
1. Z15:Z14: always ignored  
Z0: should be zero for all SPM commands, byte select for the LPM instruction.  
See “Addressing the Flash During Self-Programming” on page 275 for details about the use of  
Z-pointer during Self-Programming.  
26.9 Register Description  
26.9.1  
SPMCSR – Store Program Memory Control and Status Register  
The Store Program Memory Control and Status Register contains the control bits needed to con-  
trol the Boot Loader operations.  
Bit  
7
SPMIE  
R/W  
0
6
5
4
RWWSRE  
R/W  
3
BLBSET  
R/W  
0
2
PGWRT  
R/W  
0
1
PGERS  
R/W  
0
0
RWWSB  
SELFPRGEN  
SPMCSR  
0x37 (0x57)  
Read/Write  
Initial Value  
R
0
R
0
R/W  
0
0
• Bit 7 – SPMIE: SPM Interrupt Enable  
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM  
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-  
PRGEN bit in the SPMCSR Register is cleared.  
• Bit 6 – RWWSB: Read-While-Write Section Busy  
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-  
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section  
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a  
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be  
cleared if a page load operation is initiated.  
284  
ATmega48/88/168  
2545M–AVR–09/07  
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