ATmega8(L)
Figure 28. Timer/Counter Timing Diagram, No Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 29 shows the same timing data, but with the prescaler enabled.
Figure 29. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR0
Bit
7
–
6
–
5
–
4
–
3
–
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 2:0 – CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter.
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