ATmega8(L)
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 32. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 32. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
1
1
0
1
0
1
The low level of INT0 generates an interrupt request
Any logical change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request
The rising edge of INT0 generates an interrupt request
General Interrupt
Control Register –
GICR
Bit
7
6
5
–
4
–
3
–
2
–
1
IVSEL
R/W
0
0
IVCE
R/W
0
INT1
R/W
0
INT0
R/W
0
GICR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU
general Control Register (MCUCR) define whether the external interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
general Control Register (MCUCR) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
General Interrupt Flag
Register – GIFR
Bit
7
INTF1
R/W
0
6
INTF0
R/W
0
5
–
4
–
3
–
2
–
1
–
0
–
GIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7 – INTF1: External Interrupt Flag 1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-
bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding
Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured
as a level interrupt.
67
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
