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ATMEGA8L-8MUR 参数 Datasheet PDF下载

ATMEGA8L-8MUR图片预览
型号: ATMEGA8L-8MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位爱特梅尔带有8K字节的系统内可编程闪存 [8-bit Atmel with 8KBytes In-System PRogrammable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路异步传输模式PCATM时钟
文件页数/大小: 331 页 / 6705 K
品牌: ATMEL [ ATMEL ]
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ATmega8(L)  
Table 34. Clock Select Bit Description  
CS02  
CS01  
CS00  
Description  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped)  
clkI/O/(No prescaling)  
clkI/O/8 (From prescaler)  
clkI/O/64 (From prescaler)  
clkI/O/256 (From prescaler)  
clkI/O/1024 (From prescaler)  
External clock source on T0 pin. Clock on falling edge  
External clock source on T0 pin. Clock on rising edge  
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the  
counter even if the pin is configured as an output. This feature allows software control of the  
counting.  
Timer/Counter  
Register – TCNT0  
Bit  
7
6
5
4
3
2
1
0
TCNT0[7:0]  
TCNT0  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
The Timer/Counter Register gives direct access, both for read and write operations, to the  
Timer/Counter unit 8-bit counter.  
Timer/Counter  
Interrupt Mask  
Register – TIMSK  
Bit  
7
OCIE2  
R/W  
0
6
TOIE2  
R/W  
0
5
TICIE1  
R/W  
0
4
OCIE1A  
R/W  
0
3
OCIE1B  
R/W  
0
2
TOIE1  
R/W  
0
1
0
TOIE0  
R/W  
0
TIMSK  
Read/Write  
Initial Value  
R/W  
0
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable  
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the  
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an  
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-  
rupt Flag Register – TIFR.  
Timer/Counter  
Interrupt Flag Register  
– TIFR  
Bit  
7
OCF2  
R/W  
0
6
TOV2  
R/W  
0
5
4
OCF1A  
R/W  
0
3
OCF1B  
R/W  
0
2
TOV1  
R/W  
0
1
0
TOV0  
R/W  
0
ICF1  
R/W  
0
TIFR  
Read/Write  
Initial Value  
R/W  
0
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag  
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-  
ware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is  
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow  
Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.  
72  
2486AA–AVR–02/2013  
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