ATmega8(L)
Timer/Counter
Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located
in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see
“Timer/Counter0 and Timer/Counter1 Prescalers” on page 73.
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable counter unit. Figure 27 shows a
block diagram of the counter and its surroundings.
Figure 27. Counter Unit Block Diagram
TOVn
(Int. Req.)
DATA BUS
Clock Select
count
Edge
Detector
TCNTn
Control Logic
max
Tn
clkTn
( From Prescaler )
Signal description (internal signals):
count
clkTn
max
Increment TCNT0 by 1
Timer/Counter clock, referred to as clkT0 in the following
Signalize that TCNT0 has reached maximum value
The counter is incremented at each timer clock (clkT0). clkT0 can be generated from an external
or internal clock source, selected by the clock select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the
CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
Operation
The counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts
from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set
in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves
like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by soft-
ware. A new counter value can be written anytime.
Timer/Counter
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 28 on page 71 contains timing data for basic Timer/Counter operation. The
figure shows the count sequence close to the MAX value.
70
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
