BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag
at BOTTOM.
Figure 52. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
New OCRnx Value
Old OCRnx Value
Figure 53 shows the same timing data, but with the prescaler enabled.
Figure 53. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clk
I/O
clk
(clkT/n8)
I/O
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn(FPWM)
and ICFn(if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
124
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
