ATmega32(L)
Table 91. Boundary-scan Signals for the ADC
Recommended
Input when Not
in Use
Output Values when Recommended
Inputs are used, and CPU is not
Using the ADC
Signal
Name
Direction as Seen
from the ADC
Description
COMP
ACLK
Output
Input
Comparator Output
0
0
0
0
Clock signal to gain stages
implemented as Switch-cap filters
ACTEN
Input
Input
Enable path from gain stages to
the comparator
0
0
0
0
ADCBGEN
Enable Band-gap reference as
negative input to comparator
ADCEN
AMPEN
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power-on signal to the ADC
Power-on signal to the gain stages
Bit 9 of digital value to DAC
Bit 8 of digital value to DAC
Bit 7 of digital value to DAC
Bit 6 of digital value to DAC
Bit 5 of digital value to DAC
Bit 4 of digital value to DAC
Bit 3 of digital value to DAC
Bit 2 of digital value to DAC
Bit 1 of digital value to DAC
Bit 0 of digital value to DAC
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
Connect ADC channels 0 - 3 to by-
pass path around gain stages
G10
Input
Input
Input
Enable 10x gain
Enable 20x gain
0
0
0
0
0
0
G20
GNDEN
Ground the negative input to
comparator when true
HOLD
Input
Sample&Hold signal. Sample
analog signal when low. Hold
signal when high. If gain stages
are used, this signal must go
active when ACLK is high.
1
1
IREFEN
Input
Enables Band-gap reference as
AREF signal to DAC
0
0
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
Input
Input
Input
Input
Input
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
0
0
0
0
0
0
0
0
0
0
235
2503J–AVR–10/06
ATMEL [ ATMEL ]
