Table 92. Algorithm for Using the ADC
PA3.
PA3.
Data
PA3.
Control
Pullup_
Enable
Step
Actions
ADCEN
DAC
MUXEN
HOLD
PRECH
1
SAMPLE
_PRELO
AD
1
0x200
0x08
1
1
0
0
0
2
3
4
5
6
EXTEST
1
1
1
1
1
0x200
0x200
0x123
0x123
0x200
0x08
0x08
0x08
0x08
0x08
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Verify the
COMPbit
scanned
out to be
0
7
8
1
1
1
1
1
0x200
0x200
0x143
0x143
0x200
0x08
0x08
0x08
0x08
0x08
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
10
11
Verify the
COMPbit
scanned
out to be
1
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock
frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency
has to be at least five times the number of scan bits divided by the maximum hold time,
thold,max
.
238
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
