ATmega32(L)
regardless of any ongoing conversions. For a complete description of this bit, see “The
ADC Data Register – ADCL and ADCH” on page 217.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the
ADC. These bits also select the gain for the differential channels. See Table 84 for
details. If these bits are changed during a conversion, the change will not go in effect
until this conversion is complete (ADIF in ADCSRA is set).
Table 84. Input Channel and Gain Selections
Single Ended
Input
Positive Differential
Input
Negative Differential
Input
MUX4..0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010(1)
01011(1)
01100
01101
01110(1)
01111(1)
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
Gain
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
N/A
ADC0
ADC1
ADC0
ADC1
ADC2
ADC3
ADC2
ADC3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
ADC4
ADC0
ADC0
ADC0
ADC0
ADC2
ADC2
ADC2
ADC2
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC2
ADC2
ADC2
ADC2
ADC2
10x
10x
200x
200x
10x
10x
200x
200x
1x
1x
N/A
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
215
2503J–AVR–10/06
ATMEL [ ATMEL ]
