Table 82. Correlation between Input Voltage and Output Codes
VADCn
Read code
0x1FF
0x1FF
0x1FE
...
Corresponding Decimal Value
VADCm + VREF/GAIN
511
511
510
...
VADCm + 511/512 VREF/GAIN
VADCm + 510/512 VREF/GAIN
...
V
ADCm + 1/512 VREF/GAIN
VADCm
ADCm - 1/512 VREF/GAIN
0x001
0x000
0x3FF
...
1
0
V
-1
...
...
VADCm - 511/512 VREF/GAIN
0x201
0x200
-511
-512
VADCm - VREF/GAIN
Example:
ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right
adjusts the result: ADCL = 0x70, ADCH = 0x02.
ADC Multiplexer Selection
Register – ADMUX
Bit
7
REFS1
R/W
0
6
REFS0
R/W
0
5
ADLAR
R/W
0
4
MUX4
R/W
0
3
MUX3
R/W
0
2
MUX2
R/W
0
1
MUX1
R/W
0
0
MUX0
R/W
0
ADMUX
Read/Write
Initial Value
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 83. If these bits
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set). The internal voltage reference options may not be
used if an external reference voltage is being applied to the AREF pin.
Table 83. Voltage Reference Selections for ADC
REFS1
REFS0 Voltage Reference Selection
0
0
1
1
0
1
0
1
AREF, Internal Vref turned off
AVCC with external capacitor at AREF pin
Reserved
Internal 2.56V Voltage Reference with external capacitor at AREF pin
•
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
214
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
