ATmega16(L)
.
Table 53. Compare Output Mode, Phase Correct PWM Mode(1)
COM21 COM20 Description
0
0
1
0
1
0
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on compare match when up-counting. Set OC2 on compare
match when downcounting.
1
1
Set OC2 on compare match when up-counting. Clear OC2 on compare
match when downcounting.
Note:
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 118 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Table 54.
Table 54. Clock Select Bit Description
CS22
CS21
CS20
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped).
clkT2S/(No prescaling)
clkT2S/8 (From prescaler)
clkT2S/32 (From prescaler)
clkT2S/64 (From prescaler)
clkT2S/128 (From prescaler)
clkT S/256 (From prescaler)
2
clkT S/1024 (From prescaler)
2
Timer/Counter Register –
TCNT2
Bit
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)
the compare match on the following timer clock. Modifying the counter (TCNT2) while
the counter is running, introduces a risk of missing a compare match between TCNT2
and the OCR2 Register.
123
2466E–AVR–10/02
ATMEL [ ATMEL ]
