ATmega8U2/16U2/32U2
• Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag
This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is
enabled. WDEWIF is automatically cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag.
When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 2 - WDEWIE: Watchdog Early Warning Interrupt Enable
When this bit has been set by software, an interrupt will be generated on the watchdog interrupt
vector when the Early warning flag is set to one by hardware.
• Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider
Table 10-2. Watchdog Timer Clock Divider Configuration
WCLKD2
WCLKD1
WCLKD0
Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ClkWDT = Clk128k
ClkWDT = Clk128k / 3
ClkWDT = Clk128k / 5
ClkWDT = Clk128k / 7
ClkWDT = Clk128k / 9
ClkWDT = Clk128k / 11
ClkWDT = Clk128k / 13
ClkWDT = Clk128k / 15
Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1)
Watchdog
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
Early warning Typical
Time-out at
Reset/Interrupt Typical
Time-out at
WDP3
WDP2
WDP1
WDP0
V
CC = 5.0V
16 ms
32 ms
64 ms
0.125 s
0.25 s
0.5 s
V
CC = 5.0V
32 ms
64 ms
128 ms
0.250 s
0.5 s
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
1.0 s
1.0 s
2.0 s
2.0 s
4.0 s
4.0 s
8.0 s
8.0 s
16.0 s
58
7799D–AVR–11/10
ATMEL [ ATMEL ]
