ATmega8U2/16U2/32U2
• Bit 3 – RXSTPE: Received SETUP Interrupt Enable Flag
Writing this bit to one enables interrupt on RXSTPI flag. A receiveD setup interrupt will be gener-
ated only if the RXSTPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the RXSTPI is set.
• Bit 2 – RXOUTE: Received OUT Data Interrupt Enable Flag
Writing this bit to one enables interrupt on RXOUTI flag. A receiveD OUT interrupt will be gener-
ated only if the RXOUTE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the RXOUTI is set.
• Bit 1 – STALLEDE: Stalled Interrupt Enable Flag
Writing this bit to one enables interrupt on STALLEDI flag. A sent STALL interrupt will be gener-
ated only if the STALLEDE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the STALLEDI is set.
• Bit 0 – TXINE: Transmitter Ready Interrupt Enable Flag
Writing this bit to one enables interrupt on TXINI flag. A transmitter ready interrupt will be gener-
ated only if the TXINE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the TXINI is set.
21.18.17 UEDATX – USB Data Endpoint Register
Bit
(0xF1)
7
6
5
DAT D5
R/W
0
4
DAT D4
R/W
0
3
DAT D3
R/W
0
2
DAT D2
R/W
0
1
DAT D1
R/W
0
0
DAT D0
R/W
0
DAT D7
DAT D6
UEDATX
Read/Write
Initial Value
R/W
0
R/W
0
• Bits 7:0 – DAT[7:0]: Data Bits
The USB Data Endpoint register is a read/write register used for data transfer between the Reg-
ister File and the USB device controller. Writing to the register pushes the data byte into the
current bank of the selected endpoint. Reading the register pops extracts one data byte from the
current bank of the selected endpoint.
21.18.18 UEBCLX – USB Endpoint Byte Count Register
Bit
(0xF2)
7
6
5
4
3
2
1
0
BYCT D7
BYCT D6
BYCT D5
BYCT D4
BYCT D3
BYCT D2
BYCT D1
BYCT D0
UEBCLX
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
• Bits 7:0 – BYCT[7:0]:Byte Count Bits
This register is read only. Its content is updated by the USB controller.
• For IN endpoint:
This register contains the number of byte currently loaded into the current bank of the selected
endpoint. The content of this register is incremented after each write access to the endpoint data
register.
• For OUT endpoint:
221
7799D–AVR–11/10
ATMEL [ ATMEL ]
