ATmega8U2/16U2/32U2
• Bit 4 – STALLRQC: STALL Request Clear Handshake Bit
Writing this bit to one disables the pending STALL handshake mechanism triggered by
STALLRQ bit. This bit can not be write to zero, it is cleared by hardware immediately after the
write to one operation.
See “STALL request” on page 201 for more details.
• Bit 3 – RSTDT: Reset Data Toggle Bit
Writing this bit to one allows to reset the data toggle bit field for the selected endpoint. This bit
can not be write to zero, it is cleared by hardware immediately after the write to one operation.
• Bits 2:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPEN: Endpoint Enable Bit
Writing this bit to one enables the selected endpoint. When the endpoint is enabled it can be
configured and used by the USB controller. Endpoint 0 shall always be enabled after a hardware
or USB reset and participate in the device configuration. Writing this bit to zero disables the cur-
rent endpoint.
See “Endpoint activation” on page 198 for more details.
21.18.11 UECFG0X – USB Endpoint Configuration 0 Register
Bit
(0xEC)
7
6
5
4
-
3
-
2
-
1
-
0
EPDIR
R/W
0
EPTYPE1:0
-
UECFG0X
Read/Write
Initial Value
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
• Bit 7:6 – EPTYPE[1:0]: Endpoint Type Bits
These bits configure the endpoint type for the selected endpoint as shown in Table 21-2.
Table 21-2. EPTYPE[1:0] Bits Settings
EPTYPE1
EPTYPE0
Endpoint Type Configuration
Control Type
0
0
1
1
0
1
0
1
Isochronous Type
Bulk Type
Interrupt Type
• Bits 5:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPDIR: Endpoint Direction Bit
Writing this bit to one configures the selected endpoint in the IN direction. Writing this bit to zero
configure the endpoint in the OUT direction. This bit is relevant for bulk, interrupt or isochronous
endpoints. Using this bit with a control endpoint has no effect (control endpoints are
bidirectional).
215
7799D–AVR–11/10
ATMEL [ ATMEL ]
