• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out
data, the TDO pin drives actively. In other states the pin is pulled high.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 12-19. Overriding Signals for Alternate Functions in PF7:PF4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
PF7/ADC7/TDI
PF6/ADC6/TDO
PF5/ADC5/TMS
PF4/ADC4/TCK
JTAGEN
JTAGEN
JTAGEN
JTAGEN
1
1
1
1
JTAGEN
JTAGEN
JTAGEN
JTAGEN
0
SHIFT_IR + SHIFT_DR
0
0
0
JTAGEN
0
0
0
TDO
0
0
–
–
–
–
JTAGEN
JTAGEN
JTAGEN
JTAGEN
0
–
0
–
0
–
0
–
TDI
ADC7 INPUT
TMS
ADC5 INPUT
TCK
ADC4 INPUT
AIO
ADC6 INPUT
84
ATmega169P
8018A–AVR–03/06
ATMEL [ ATMEL ]
