ATmega169P
• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in Table 22-5 on page 247. This Clock Divider gives extra flexibility in frame rate
selection.
Table 22-5. LCD Clock Divide
Output from Prescaler
divided by (D):
clkLCD = 32.768 kHz, N = 16, and
Duty = 1/4, gives a frame rate of:
LCDCD2
LCDCD1
LCDCD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
256 Hz
128 Hz
85.3 Hz
64 Hz
51.2 Hz
42.7 Hz
36.6 Hz
32 Hz
The frame frequency can be calculated by the following equation:
f
clkLCD
f
= -------------------------
frame
(K ⋅ N ⋅ D)
Where:
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see Table 22-5).
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
is increased with 33ꢀ when Frame Rate Register is constant. Example of frame rate calculation
is shown in Table 22-6.
Table 22-6. Example of frame rate calculation
clkLCD
duty
1/4
K
N
LCDCD2:0
011
D
Frame Rate
4 MHz
8
6
8
8
2048
4
4
1
5
4000000/(8*2048*4) = 61 Hz
4000000/(6*2048*4) = 81 Hz
32768/(8*16*1) = 256 Hz
32768/(8*16*5) = 51 Hz
4 MHz
1/3
2048
16
011
32.768 kHz
32.768 kHz
Static
1/2
000
16
100
247
8018A–AVR–03/06
ATMEL [ ATMEL ]
