ATmega169P
16.5.1
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the
OC2A Register is to be performed on the next compare match. For compare output actions in
the non-PWM modes refer to Table 16-3 on page 154. For fast PWM mode, refer to Table 16-4
on page 154, and for phase correct PWM refer to Table 16-5 on page 154.
A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2A strobe bits.
16.6 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output
mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM
output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM
modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a
compare match (See ”Compare Match Output Unit” on page 142.).
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 148.
16.6.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
16.6.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT2)
increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.
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8018A–AVR–03/06
ATMEL [ ATMEL ]
