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ATMEGA128L-8AL 参数 Datasheet PDF下载

ATMEGA128L-8AL图片预览
型号: ATMEGA128L-8AL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 391 页 / 6192 K
品牌: ATMEL [ ATMEL ]
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Stack Pointer  
The Stack is mainly used for storing temporary data, for storing local variables and for storing  
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points  
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-  
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack  
Pointer.  
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt  
Stacks are located. This Stack space in the data SRAM must be defined by the program before  
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to  
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack  
with the PUSH instruction, and it is decremented by two when the return address is pushed onto  
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is  
popped from the Stack with the POP instruction, and it is incremented by two when data is  
popped from the Stack with return from subroutine RET or return from interrupt RETI.  
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of  
bits actually used is implementation dependent. Note that the data space in some implementa-  
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register  
will not be present.  
Bit  
15  
SP15  
SP7  
7
14  
SP14  
SP6  
6
13  
SP13  
SP5  
5
12  
SP12  
SP4  
4
11  
SP11  
SP3  
3
10  
SP10  
SP2  
2
9
SP9  
SP1  
1
8
SP8  
SP0  
0
SPH  
SPL  
Read/Write  
Initial Value  
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
0
0
0
0
0
0
0
0
RAM Page Z Select  
Register – RAMPZ  
Bit  
7
6
––  
R
5
4
3
2
1
0
RAMPZ0  
R/W  
RAMPZ  
Read/Write  
Initial Value  
R
0
R
0
R
0
R
0
R
0
R
0
0
0
• Bits 7..1 – Res: Reserved Bits  
These are reserved bits and will always read as zero. When writing to this address location,  
write these bits to zero for compatibility with future devices.  
• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer  
The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-  
pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is  
used only to select which page in the program memory is accessed when the ELPM/SPM  
instruction is used. The different settings of the RAMPZ0 bit have the following effects:  
RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is  
accessed by ELPM/SPM  
RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is  
accessed by ELPM/SPM  
Note that LPM is not affected by the RAMPZ setting.  
Instruction  
Execution Timing  
This section describes the general access timing concepts for instruction execution. The AVR  
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the  
chip. No internal clock division is used.  
14  
ATmega128(L)  
2467P–AVR–08/07  
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